# Physical Design Flow & Methodology Engineer > quadric, Inc · Pune, India · Full-time · Posted 2026-04-03 **Workplace:** on_site **Department:** Hardware Engineering ## Description Quadric delivers its GPNPU as soft IP — RTL and implementation collateral — enabling customers to integrate our processor into their own SoCs across a range of process nodes and foundries. You will drive PPA optimization across IP configurations, build the scalable reference flows customers use to evaluate and integrate our IP, and provide hands-on implementation support to customers working toward their tapeouts. ### Responsibilities ### PPA Optimization & Analysis - Drive PPA analysis and optimization for Quadric GPNPU soft IP across process nodes and hardware configurations — timing, area, leakage, and dynamic power - Apply low-power techniques (clock gating, multi-Vt, operand isolation) and synthesis/P&R knobs to hit frequency and area targets - Characterize the IP design space across configurations and build PPA models that support customer evaluations and pre-sales engagements - Partner with RTL and architecture teams early to quantify tradeoffs and influence design decisions before they become costly to reverse ### Reference Flow Development - Build and maintain a scalable RTL-to-GDS reference flow for Quadric soft IP that customers can use to evaluate, integrate, and close PPA in their own SoC environment - Ensure the flow is portable across supported process nodes with clear BKMs, SDC templates, floorplan scripts, and integration guidelines - Develop TCL and Python automation — and leverage AI coding tools such as Claude — to accelerate flow development, reduce manual effort, and improve repeatability - Qualify EDA tool updates and benchmark QoR impact before rolling into the reference flow ### Customer Integration & Tapeout Support - Act as the primary PD contact for customers integrating Quadric soft IP, guiding them from evaluation through their SoC tapeout - Help customers adapt the reference flow to their process node, foundry PDK, and internal design environment - Triage and resolve customer-reported implementation issues — timing, congestion, power, or flow failures — working with internal teams to deliver fixes or updated collateral - Support FAE and business development with PPA feasibility studies for new customer engagements ### Collaboration & Documentation - Work with architecture, RTL, and software teams to ensure IP deliverables meet customer-facing PPA targets - Document methodologies, BKMs, and optimization learnings; maintain process node bring-up guidelines to support IP portability ## Requirements ### Education & Experience - BS/MS in Electrical Engineering, Computer Engineering, or related field - 4+ years of ASIC or processor IP physical design experience focused on PPA optimization and flow development across advanced nodes ### Technical Skills - Proficiency with industry-standard physical design tools from Synopsys or Cadence (synthesis, place-and-route, and timing analysis) - Experience with advanced FinFET process nodes (16nm and below); multi-node experience preferred - Strong TCL scripting and Python automation skills - Solid understanding of synthesis and P&R levers for PPA — timing paths, cell selection, congestion, and power intent - Hands-on experience with low-power design techniques and MCMM timing analysis - Comfort using AI tools (e.g., Claude, Copilot) to accelerate script development, automate repetitive EDA tasks, and improve workflow productivity - Understanding of DFT concepts (scan, ICG bypass) and their physical design implications ### Nice to Have - Experience delivering soft IP to external customers or supporting SoC integrators through tapeout - Background in AI accelerator, NPU, or DSP processor IP implementation - Exposure to metrics-driven QoR tracking and large-scale synthesis run management ## Apply [Apply at quadric, Inc](https://apply.workable.com/quadric-dot-i-o-inc/j/B35A0ECF58/apply) --- Powered by [Workable](https://www.workable.com)