# Analog Layout Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-08-20

**Salary:** INR 2,900,000–9,000,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟵𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟵𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟵-𝟵𝟬 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for an experienced **Analog Layout Engineer** with 4+ years of hands-on experience in **custom IC and analog/mixed-signal layout**. The role involves developing high-quality layouts for complex analog circuits, performing physical verification, and supporting designs through the complete layout lifecycle from schematic implementation to final GDS delivery.

The ideal candidate will have strong expertise in **Cadence Virtuoso, analog layout techniques, physical verification, device matching, parasitic management, and advanced semiconductor process technologies**. You will work closely with circuit designers, verification engineers, and physical design teams to achieve performance, area, reliability, and manufacturability targets.

## Requirements

### Key Responsibilities

-   Develop **full-custom analog and mixed-signal layouts** for complex semiconductor designs.
-   Translate schematics into optimized physical layouts from initial placement through **final GDS delivery**.
-   Perform critical layout techniques including **placement, routing, shielding, common-centroid layouts, interdigitation, matching, guard rings, and symmetry**.
-   Design layouts for blocks such as **amplifiers, ADC/DAC, PLLs, bandgaps, voltage references, LDOs**, and other analog circuits.
-   Execute and debug **DRC, LVS, ERC, and PEX** checks and resolve physical verification issues.
-   Analyze and minimize the impact of **parasitics, mismatch, coupling, and layout-dependent effects**.
-   Work closely with circuit designers to meet **performance, area, power, reliability, and matching requirements**.
-   Support **post-layout simulation** and investigate layout-related performance degradation.
-   Ensure layouts comply with **foundry PDKs, technology-specific requirements, and design rules**.
-   Apply appropriate techniques for **ESD, latch-up prevention, isolation, shielding, and noise reduction**.
-   Collaborate with verification and physical design teams throughout the development and sign-off process.
-   Contribute to design reviews, layout quality improvements, and efficient implementation methodologies.

### What's Makes You a Great Fit

-   **4+ years of professional experience** in analog/custom IC layout.
-   Strong hands-on experience with **analog and mixed-signal layout**.
-   Proficiency in **Cadence Virtuoso** and industry-standard physical verification tools.
-   Strong understanding of **DRC, LVS, ERC, PEX**, and physical verification debugging.
-   Experience with **FinFET and/or planar/non-FinFET semiconductor technologies**.
-   Strong knowledge of **device matching, common-centroid techniques, shielding, guard rings, parasitics, symmetry, and routing methodologies**.
-   Understanding of **ESD, latch-up, reliability, and layout-dependent effects**.
-   Experience working with **advanced semiconductor process nodes** is an advantage.
-   Ability to interpret schematics and collaborate effectively with **circuit designers and verification teams**.
-   Strong debugging, analytical, and problem-solving capabilities.
-   High attention to detail with a strong focus on **layout quality, accuracy, and sign-off readiness**.
-   Ability to manage multiple layout tasks and deliver high-quality work within project timelines.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/0E44ED0FB4/apply)

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