# Analog Layout

> Weekday AI · Hyderabad, India · Full-time · Posted 2026-07-14

**Salary:** INR 1,200,000–3,000,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

**Salary range: Rs 1200000 - Rs 3000000 (ie INR 12-30 LPA)**

Min Experience: 3+ years

Location: Hyderabad

JobType: full-time

We are looking for a highly motivated **Analog Layout Engineer** with **3–10 years of experience** in custom analog and mixed-signal IC layout. The ideal candidate will have strong expertise in advanced semiconductor process technologies, particularly **TSMC 2nm and TSMC 3nm**, and hands-on experience designing high-performance layouts for **PLL, ADC, and DAC** circuits. In this role, you will work closely with circuit designers, verification engineers, and physical design teams to develop robust, manufacturable, and high-performance analog layouts for next-generation semiconductor products.

This is an exciting opportunity to contribute to cutting-edge silicon development while solving complex layout challenges in advanced technology nodes.

## Requirements

### Key Responsibilities

-   Design and implement custom analog and mixed-signal layouts for high-performance integrated circuits.
-   Develop layouts for critical analog IPs, including **Phase-Locked Loops (PLL), Analog-to-Digital Converters (ADC), and Digital-to-Analog Converters (DAC)**.
-   Execute layouts using **TSMC 2nm and TSMC 3nm** process technologies while adhering to foundry design rules and reliability requirements.
-   Optimize layouts for matching, symmetry, parasitic reduction, signal integrity, and overall circuit performance.
-   Collaborate closely with analog circuit designers to understand design intent and ensure layout accuracy.
-   Perform layout verification, including DRC, LVS, ERC, and parasitic extraction, ensuring first-pass silicon success.
-   Resolve physical design challenges associated with advanced nodes, including electromigration, IR drop, density, and reliability concerns.
-   Support tape-out activities and coordinate with verification and manufacturing teams to achieve project milestones.
-   Contribute to layout methodology improvements, automation initiatives, and best practices for advanced technology nodes.
-   Document layout methodologies and provide technical support during silicon bring-up and post-silicon analysis.

### Required Qualifications

-   Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or a related discipline.
-   **3–10 years of experience** in analog or mixed-signal IC layout design.
-   Strong expertise in **TSMC 2nm and TSMC 3nm** process technologies.
-   Proven experience in the layout of **PLL, ADC, and DAC** circuits.
-   Deep understanding of analog layout techniques including common-centroid structures, interdigitation, matching, shielding, guard rings, isolation, and routing optimization.
-   Hands-on experience with industry-standard layout tools such as Cadence Virtuoso and physical verification environments.
-   Strong knowledge of DRC, LVS, ERC, parasitic extraction, and physical verification methodologies.
-   Familiarity with reliability considerations such as electromigration, ESD protection, latch-up prevention, and process variation.
-   Excellent debugging and problem-solving skills with attention to layout quality and manufacturability.
-   Strong communication skills and the ability to work effectively in cross-functional engineering teams.

### Preferred Skills

-   Experience working on high-speed analog and mixed-signal IP development.
-   Exposure to FinFET or Gate-All-Around (GAA) technologies in advanced process nodes.
-   Knowledge of low-power and high-performance layout optimization techniques.
-   Experience supporting multiple tape-outs in advanced semiconductor technologies.
-   Familiarity with scripting languages such as SKILL, Python, or Perl for layout automation.
-   Understanding of semiconductor manufacturing processes and yield enhancement methodologies.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/19EC17632B/apply)

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