# Design For Test - Lead

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-07-10

**Salary:** INR 4,500,000–6,500,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

**Salary range: Rs 4500000 - Rs 6500000 (ie INR 45-65 LPA)**

Experience: 7+ yrs

Location: Bengaluru

Job Type: Full-Time

We are seeking an experienced **DFT Engineer** to lead the Design for Test (DFT) implementation for complex SoC designs. This role requires strong expertise in defining DFT architecture, implementing and verifying DFT methodologies, and supporting the complete silicon lifecycle from architecture through post-silicon validation. The ideal candidate will have hands-on experience with hierarchical SoC DFT implementation, test optimization, and industry-standard DFT tools while collaborating closely with Product Engineering, RTL, STA, Physical Design, and Verification teams.

## Requirements

### Key Responsibilities

-   Define and implement DFT architecture for complex SoC designs, optimizing test coverage, test time, test cost, and test power.
-   Plan, track, and execute end-to-end DFT implementation across hierarchical SoC projects.
-   Implement and verify Scan, ATPG, MBIST, Boundary Scan, and other DFT methodologies.
-   Perform DFT logic integration, verification, and debugging to ensure high-quality test implementation.
-   Analyze and improve test coverage by identifying and resolving low coverage issues.
-   Execute gate-level DFT verification with and without timing to validate test functionality.
-   Generate, verify, and deliver production-ready test patterns to ATE teams.
-   Support post-silicon bring-up, debug failing patterns, and assist in silicon validation activities.
-   Provide DFT mode STA support and contribute to timing closure activities.
-   Collaborate with cross-functional engineering teams to ensure successful tape-out and production readiness.
-   Mentor junior engineers and contribute to improving DFT methodologies, workflows, and best practices.

### What Makes You a Great Fit

-   Proven experience leading DFT implementation for multiple successful ASIC/SoC tape-outs.
-   Strong expertise in **DFT Architecture, Scan, ATPG, MBIST, Boundary Scan, and DFT Integration**.
-   Hands-on experience with gate-level DFT verification, pattern generation, and coverage analysis.
-   Strong debugging skills for low test coverage, failing patterns, and post-silicon validation issues.
-   Experience supporting DFT mode STA and timing closure.
-   Proficiency with industry-standard DFT tools such as **Tessent, Synopsys DFT Compiler**, or equivalent EDA solutions.
-   Good understanding of hierarchical SoC DFT implementation and verification methodologies.
-   Strong analytical, troubleshooting, and problem-solving skills with a focus on silicon quality.
-   Experience leading or mentoring small DFT teams is an added advantage.
-   Excellent communication and collaboration skills to work effectively across multidisciplinary engineering teams.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/62C3E364E1/apply)

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