# RTL Micro Architect Lead

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-08-06

**Salary:** INR 2,700,000–6,700,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟳𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟲𝟳𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟳-𝟲𝟳 𝗟𝗣𝗔)

Experience: 8+ yrs

Location: Bengaluru

Job Type: Full-time

We are seeking an experienced **RTL Micro Architect Lead** to drive the microarchitecture definition and RTL development of high-performance hardware subsystems for next-generation System-on-Chip (SoC) platforms. This role is ideal for professionals with deep expertise in RTL design, digital architecture, and subsystem integration who are passionate about building cutting-edge GPU, DSP, AI accelerator, and high-performance computing solutions.

As an RTL Micro Architect Lead, you will be responsible for defining microarchitecture specifications, leading RTL implementation, and driving architectural decisions that optimize Performance, Power, and Area (PPA). You will collaborate closely with architecture, verification, firmware, physical design, and SoC integration teams to deliver scalable, high-quality hardware designs while mentoring engineers and establishing engineering best practices throughout the development lifecycle.

## Requirements

### Key Responsibilities

-   Define, own, and review microarchitecture specifications for complex digital hardware blocks and subsystems.
-   Lead RTL design, implementation, optimization, and integration using Verilog and SystemVerilog.
-   Drive architecture trade-offs to achieve optimal Performance, Power, and Area (PPA) targets.
-   Review design specifications, RTL code, and technical documentation to ensure design quality and compliance with engineering standards.
-   Collaborate with architecture, verification, firmware, physical design, and SoC integration teams throughout the product development lifecycle.
-   Support subsystem integration, timing closure, power optimization, silicon bring-up, and post-silicon debugging activities.
-   Analyze design challenges, identify performance bottlenecks, and recommend architectural improvements.
-   Participate in technical design reviews, architecture discussions, and engineering planning activities.
-   Mentor RTL engineers, provide technical guidance, and promote best practices in digital design and microarchitecture.
-   Contribute to continuous improvement initiatives focused on design methodologies, RTL quality, and engineering productivity.

### What Makes You a Great Fit

-   8+ years of experience in **RTL Design**, **Digital Design**, or **Microarchitecture Development**.
-   Strong expertise in **Verilog** and **SystemVerilog** with hands-on experience developing complex RTL designs.
-   Proven experience designing high-performance SoCs, hardware accelerators, or advanced digital subsystems.
-   Strong understanding of digital design methodologies, subsystem integration, and hardware development workflows.
-   Experience leading architecture discussions, technical decision-making, and RTL implementation efforts.
-   Knowledge of **GPU, DSP, AI accelerator**, or other compute-intensive hardware architectures is highly desirable.
-   Solid understanding of memory hierarchy, cache coherency, high-speed interconnects, and on-chip communication protocols.
-   Experience optimizing designs for **Performance, Power, and Area (PPA)**, timing closure, and silicon bring-up.
-   Excellent analytical, debugging, and problem-solving skills with the ability to resolve complex hardware design challenges.
-   Strong leadership, mentoring, communication, and cross-functional collaboration skills with a passion for delivering high-quality silicon and engineering excellence.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/7105550A55/apply)

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