# Physical Design Engineer (PNR)

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-08-06

**Salary:** INR 1,000,000–1,500,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients  
Salary range: Rs 1000000 - Rs 1500000 (ie INR 10 - 15 LPA)  
**

Min Experience: 2+ years

Location: Bengaluru  
JobType: full-time

We are looking for a talented **Physical Design Engineer (PNR)** with **2–6 years of experience** in ASIC physical design to join our semiconductor engineering team. The ideal candidate should have hands-on expertise across the complete physical design flow, with strong proficiency in **Floorplanning, Power Planning, Placement, Clock Tree Synthesis (CTS), and Place & Route (PNR)**. You will work closely with front-end design, timing, DFT, and verification teams to deliver high-performance, power-efficient, and manufacturable chip designs for advanced technology nodes.

This role offers an opportunity to work on cutting-edge semiconductor products while contributing to challenging design implementations and optimization activities.

## Requirements

### Key Responsibilities

-   Execute complete **Place & Route (PNR)** flow for complex ASIC and SoC designs.
-   Develop and optimize **floorplans** considering performance, congestion, power, and area constraints.
-   Perform **power planning**, including power grid design, IR drop considerations, and power integrity optimization.
-   Carry out standard cell **placement** with a focus on timing, congestion, and routability.
-   Implement **Clock Tree Synthesis (CTS)** to achieve timing closure while minimizing clock skew and latency.
-   Perform routing, design optimization, and engineering change orders (ECOs) to meet design objectives.
-   Analyze and resolve timing violations across setup, hold, and signal integrity constraints.
-   Collaborate with RTL, DFT, timing, and verification teams throughout the implementation cycle.
-   Support physical verification activities including DRC, LVS, antenna, and electrical rule checks.
-   Optimize designs for power, performance, and area (PPA) while ensuring high-quality implementation.
-   Debug implementation issues and recommend improvements to enhance design efficiency and productivity.
-   Maintain implementation documentation and participate in design reviews.

### Must-Have Skills

-   Strong expertise in **Place & Route (PNR)** methodologies.
-   Hands-on experience in **Floorplanning** for ASIC/SoC designs.
-   Experience in **Power Planning** and power grid implementation.
-   Proficiency in standard cell **Placement** optimization.
-   Strong knowledge of **Clock Tree Synthesis (CTS)** and timing optimization.
-   Good understanding of timing closure methodologies and static timing analysis concepts.
-   Familiarity with physical verification and signoff requirements.
-   Knowledge of advanced semiconductor design flows and physical design methodologies.
-   Strong analytical and debugging skills with attention to design quality.
-   Excellent communication and teamwork abilities.

### Good-to-Have Skills

-   Experience with advanced technology nodes (16nm, 7nm, 5nm, or below).
-   Exposure to low-power implementation techniques.
-   Knowledge of IR drop, electromigration (EM), and signal integrity analysis.
-   Familiarity with scripting using Tcl, Perl, or Python for design automation.
-   Understanding of ECO implementation and timing closure methodologies.
-   Experience with industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, PrimeTime, or similar.

### Experience

-   **2–6 years** of hands-on experience in ASIC Physical Design and PNR implementation.

### Preferred Qualifications

-   Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI Design, or a related discipline.
-   Strong understanding of semiconductor design concepts and implementation methodologies.
-   Ability to work in a collaborative, fast-paced engineering environment with cross-functional teams.
-   Passion for solving complex implementation challenges and delivering high-quality silicon.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/7E01680EFE/apply)

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