# SoC Design Verification Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-09-02

**Salary:** INR 1,600,000–6,800,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟲𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟲𝟴𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟲-𝟲𝟴 𝗟𝗣𝗔)

Experience: 4+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for a skilled **SoC Design Verification Engineer** with strong hands-on expertise in **PCIe Gen5 protocol verification** to contribute to pre-silicon verification of complex semiconductor designs.

The role involves verifying PCIe functionality across **IP, subsystem, SoC, and full-chip levels** using SystemVerilog and UVM. The ideal candidate will have strong protocol knowledge, excellent debugging capabilities, and experience driving verification coverage and sign-off for complex SoC designs.

## Requirements

### Key Responsibilities

-   Develop detailed **verification plans, test scenarios, and test strategies** for PCIe Gen5 functionality.
-   Build, enhance, and maintain **SystemVerilog/UVM-based verification environments**.
-   Verify PCIe protocol functionality across IP, subsystem, SoC, and full-chip levels.
-   Validate key PCIe features including **LTSSM, link training, TLP, DLLP, enumeration, configuration, and error handling**.
-   Perform functional, protocol compliance, and integration-level verification.
-   Develop **SystemVerilog Assertions (SVA)** and functional coverage models.
-   Execute simulation regressions and analyze failures to drive coverage closure.
-   Debug complex **PCIe protocol, RTL, and integration issues** across multiple design levels.
-   Collaborate closely with RTL designers, architects, firmware engineers, and other verification teams.
-   Identify verification gaps and contribute to improving test environments, methodologies, and automation.
-   Track coverage, defects, and verification progress throughout the project lifecycle.
-   Support **SoC/full-chip verification sign-off** and ensure verification objectives are achieved before tape-out.

### What Makes You a Great Fit

-   **4+ years of experience** in semiconductor design verification or a related field.
-   **Mandatory: Strong hands-on experience in PCIe Gen5 protocol verification.**
-   Strong proficiency in **SystemVerilog and UVM**.
-   Proven experience in **SoC/full-chip pre-silicon verification**.
-   Strong understanding of PCIe architecture and protocol concepts, including **LTSSM, TLP, DLLP, link training, enumeration, configuration, and error handling**.
-   Strong hands-on experience with **protocol-level debugging** and RTL issue analysis.
-   Experience developing verification plans, test scenarios, assertions, functional coverage, and regression environments.
-   Demonstrated ability to drive **coverage closure and verification sign-off**.
-   Strong analytical and problem-solving skills with excellent attention to detail.
-   Ability to collaborate effectively with **RTL, architecture, firmware, and cross-functional verification teams**.
-   Experience working on complex SoC or high-speed interface verification projects is highly desirable.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/91D90AE510/apply)

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