# SoC Block Integration Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-07-16

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

Min Experience: 2+ years

Location: Bengaluru  
JobType: full-time

We are looking for a talented **SoC Integration Engineer** to join our VLSI design team. In this role, you will be responsible for integrating complex SoC subsystems and IPs, ensuring seamless RTL integration, synthesis readiness, and design quality. You will work closely with Design, Verification, DFT, and Physical Design teams to deliver robust, high-performance SoC designs while ensuring compliance with lint, CDC, and low-power verification requirements.

## Requirements

### Key Responsibilities

-   Perform RTL integration of SoC blocks and third-party IPs into top-level designs.
-   Execute and resolve **SpyGlass Lint**, **Clock Domain Crossing (CDC)**, and low-power verification issues.
-   Perform RTL synthesis using **Synopsys Design Compiler (DC)** and analyze synthesis reports.
-   Develop and maintain timing constraints (SDC) to support synthesis and timing closure.
-   Debug RTL integration issues using **Verdi** or equivalent debugging tools.
-   Collaborate with Verification, Physical Design, DFT, and Architecture teams to ensure smooth project execution.
-   Identify and resolve integration, connectivity, reset, clocking, and interface issues.
-   Support design reviews and ensure adherence to coding guidelines and integration methodologies.
-   Develop scripts to automate integration, verification, and build processes where applicable.
-   Document integration procedures, constraints, and design changes throughout the development cycle.

### Required Qualifications

-   Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, Computer Engineering, or a related field.
-   4–8 years of experience in SoC Block Integration or RTL Integration.
-   Strong hands-on experience with **SpyGlass Lint**, **CDC**, **Synopsys Design Compiler (DC)**, and **VCLP**.
-   Good understanding of RTL synthesis and timing constraints using **SDC**.
-   Strong coding skills in **Verilog**, **SystemVerilog**, or **VHDL**.
-   Experience with **Verdi** or equivalent RTL debugging tools.
-   Good understanding of SoC integration methodologies, clocking, resets, and interface protocols.
-   Excellent debugging, analytical, and problem-solving skills.
-   Strong communication and collaboration skills with cross-functional engineering teams.

### Must-Have Skills

-   SoC Block Integration
-   SpyGlass Lint
-   Clock Domain Crossing (CDC)
-   Synopsys Design Compiler (DC)
-   VCLP
-   RTL Integration
-   Verilog
-   SystemVerilog
-   VHDL

### Good-to-Have Skills

-   Timing Constraints (SDC)
-   Verdi
-   RTL Synthesis
-   Low Power Verification
-   TCL/Shell Scripting
-   DFT Collaboration
-   Physical Design Flow
-   ASIC/SoC Development
-   RTL Debugging

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/927133CF94/apply)

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