# GLS engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-07-21

**Salary:** INR 1,500,000–3,000,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

**Salary range: Rs 1500000 - Rs 3000000 (ie INR 15- 30 LPA)**

Min Experience: 4+ years

Location: Bengaluru  
JobType: full-time

We are looking for a detail-oriented **GLS Engineer** with 4–5 years of experience in digital design verification and gate-level simulation. The ideal candidate will have strong expertise in **Design Verification** using **SystemVerilog** and hands-on experience with Gate-Level Simulation (GLS) to validate complex ASIC/SoC designs. You will work closely with design, verification, DFT, synthesis, STA, and physical design teams to ensure functional correctness and timing closure of high-performance semiconductor products.

This role is ideal for engineers who enjoy solving challenging verification problems, debugging complex hardware issues, and ensuring first-pass silicon success through rigorous validation methodologies.

## Requirements

### Key Responsibilities

-   Develop, execute, and maintain comprehensive verification plans for digital IPs, subsystems, and SoCs.
-   Perform gate-level simulations to validate synthesized and post-layout netlists under different operating conditions.
-   Develop and maintain SystemVerilog-based verification environments, testbenches, and reusable verification components.
-   Analyze simulation failures, timing violations, race conditions, X-propagation issues, reset behavior, and clock-related problems.
-   Collaborate with RTL designers to debug functional and timing-related issues throughout the design lifecycle.
-   Work closely with DFT, STA, synthesis, and physical design teams to resolve GLS-related challenges.
-   Execute regression suites, analyze coverage metrics, and improve verification completeness.
-   Support low-power verification, reset sequencing, initialization, and power-aware simulation activities.
-   Review design specifications and verification plans to ensure complete functional coverage.
-   Automate verification workflows using scripting languages to improve simulation efficiency and regression management.
-   Participate in design reviews, bug triage meetings, and root cause analysis for silicon bring-up issues.
-   Maintain detailed documentation of verification methodologies, test results, and debugging procedures.

### Required Qualifications

-   Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related discipline.
-   4–5 years of hands-on experience in ASIC or SoC Design Verification.
-   Strong understanding of digital design fundamentals, RTL design concepts, and verification methodologies.
-   Experience working with complex digital systems including processors, memory interfaces, buses, and peripheral IPs.
-   Excellent debugging and analytical skills with the ability to identify and resolve complex verification issues.
-   Strong communication and collaboration skills for working across multidisciplinary engineering teams.

### Must-Have Skills

-   Strong experience in **Design Verification** for ASIC/SoC development.
-   Expertise in **SystemVerilog** for writing verification environments, assertions, testbenches, and simulation infrastructure.
-   Experience with constrained-random verification methodologies.
-   Strong debugging skills involving waveform analysis and simulation log analysis.
-   Familiarity with verification planning, functional coverage, and regression management.
-   Understanding of timing concepts, clock domains, reset architecture, and digital logic verification.
-   Experience using industry-standard EDA simulation and verification tools.

### Good-to-Have Skills

-   Hands-on experience with **Gate-Level Simulation (GLS)** including post-synthesis and post-layout verification.
-   Exposure to SDF back-annotation, timing verification, and X-propagation analysis.
-   Knowledge of UVM (Universal Verification Methodology).
-   Experience with Perl, Python, TCL, or Shell scripting for automation.
-   Familiarity with DFT verification, scan testing, and ATPG concepts.
-   Exposure to static timing analysis (STA) and synthesis flows.
-   Knowledge of low-power verification methodologies such as UPF/CPF.
-   Experience with CI/CD workflows for verification regression automation.

### Preferred Attributes

-   Strong problem-solving mindset with attention to detail.
-   Ability to work independently while collaborating effectively with cross-functional teams.
-   Excellent time management and prioritization skills in fast-paced development environments.
-   Passion for delivering high-quality silicon through robust verification methodologies.
-   Continuous learning attitude with a desire to stay current on evolving verification techniques and semiconductor technologies.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/93EC7721EC/apply)

---
Powered by [Workable](https://www.workable.com)