# Design Verification Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-07-09

**Salary:** INR 400,000–4,500,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

**Salary range: Rs 400000 - Rs 4500000 (ie INR 4-45 LPA)**

Min Experience: 5+ years

Location: Bengaluru, India, Hyderabad

JobType: full-time

We are looking for an experienced **Design Verification Engineer** to join our semiconductor engineering team and contribute to the verification of next-generation digital designs. The ideal candidate will have strong expertise in **UVM (Universal Verification Methodology)** and **SystemVerilog**, with hands-on experience developing scalable verification environments for complex SoC, ASIC, or IP designs. This role offers the opportunity to work closely with design, architecture, and validation teams to ensure high-quality silicon through comprehensive verification methodologies.

If you are passionate about digital design verification, enjoy solving challenging hardware problems, and have experience building reusable verification frameworks, we'd love to hear from you.

## Requirements

### Key Responsibilities

-   Develop and execute verification plans for complex digital IPs, subsystems, and SoCs.
-   Build robust, reusable, and scalable verification environments using **UVM** and **SystemVerilog**.
-   Design constrained-random and directed test cases to validate functional correctness across various design scenarios.
-   Create reusable verification components, scoreboards, monitors, checkers, assertions, and coverage models.
-   Perform functional, code, and assertion coverage analysis to ensure complete verification closure.
-   Debug RTL issues by analyzing simulation failures, waveform traces, and log files while collaborating with design engineers.
-   Participate in architecture and design reviews to identify verification requirements early in the development cycle.
-   Automate verification workflows and improve regression efficiency through scripting and process optimization.
-   Support integration, subsystem, and SoC-level verification activities.
-   Document verification strategies, test plans, and verification results while maintaining engineering best practices.

### Required Skills

-   Strong expertise in **UVM (Universal Verification Methodology)**.
-   Excellent hands-on experience with **SystemVerilog** for verification.
-   Deep understanding of digital logic design and verification methodologies.
-   Experience developing reusable verification environments for ASIC, SoC, or IP verification.
-   Strong debugging and problem-solving abilities using simulation and waveform analysis tools.
-   Good understanding of constrained-random verification, assertions, functional coverage, and regression methodologies.
-   Familiarity with verification planning and verification closure processes.
-   Ability to work effectively within cross-functional engineering teams.

### Good-to-Have Skills

-   Experience verifying **PCIe (PCI Express)** based designs and protocols.
-   Knowledge of advanced **Design Verification** methodologies and verification automation.
-   Understanding of **VLSI** design and semiconductor development lifecycle.
-   Exposure to industry-standard simulators, linting, formal verification, or emulation platforms.
-   Experience with scripting languages such as Python, Perl, TCL, or Shell for automation.
-   Familiarity with additional high-speed protocols and interface standards is a plus.

### Qualifications

-   Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related discipline.
-   **5–18 years** of professional experience in digital design verification.
-   Proven experience delivering verification for complex semiconductor products from specification through silicon validation.
-   Strong communication, analytical thinking, and collaboration skills.

### What You'll Bring

The ideal candidate combines strong technical expertise with a quality-first mindset. You are comfortable working on challenging verification problems, collaborating with multidisciplinary engineering teams, and continuously improving verification methodologies. Your experience in building reusable verification environments using UVM and SystemVerilog, along with your understanding of modern VLSI verification practices, will enable you to contribute to the successful delivery of reliable, high-performance semiconductor products.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/9D455CA12F/apply)

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