# Senior RTL Integration Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-09-16

**Salary:** INR 2,500,000–4,000,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟮𝟱𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟰𝟬𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟮𝟱-𝟰𝟬 𝗟𝗣𝗔)

Experience: 7+ yrs

Location: Bengaluru, Karnataka

Job Type: Full-time

We are looking for an experienced **Senior RTL Integration Engineer** to lead the integration of complex RTL designs and third-party IPs for advanced **SoC and semiconductor products**. This role requires strong hands-on expertise in **RTL Integration and Verilog**, along with a solid understanding of digital design, SoC architecture, interconnects, clocking, resets, and design-quality methodologies.

The ideal candidate will be responsible for integrating large and complex RTL blocks, ensuring connectivity and functionality, resolving integration issues, and supporting the design through verification, synthesis, physical design, and tapeout. You will collaborate closely with Architecture, Design Verification, DFT, Synthesis, Physical Design, and other engineering teams to deliver high-quality silicon-ready designs.

## Requirements

### KEY RESPONSIBILITIES

-   Lead **RTL integration** for complex SoCs, subsystems, and multi-million-gate designs.
-   Integrate internal and third-party IPs using **Verilog/SystemVerilog** and established integration methodologies.
-   Develop and maintain RTL connectivity between processors, memories, interconnects, peripherals, and subsystem interfaces.
-   Work with protocols including **AMBA AXI4, AHB, APB, and related interconnect standards**.
-   Integrate IPs such as **PCIe, DDR, Ethernet, ARM/RISC-V processors**, and other SoC components.
-   Handle clock, reset, configuration, power, and connectivity requirements across integrated designs.
-   Perform RTL quality checks including **lint, CDC, RDC, and structural verification**.
-   Work with tools such as SpyGlass, Questa CDC, VC SpyGlass, or equivalent static-analysis platforms.
-   Develop and review **SDC timing constraints** and collaborate with Synthesis and Physical Design teams on timing requirements.
-   Analyse synthesis, timing, area, and power results and resolve RTL-level integration issues.
-   Implement functional and timing **ECOs** while maintaining design integrity.
-   Develop automation scripts using **Python, TCL, Perl, or Shell** to improve RTL integration and verification workflows.
-   Debug complex RTL, connectivity, simulation, synthesis, and integration issues.
-   Participate in architecture, design, code, and sign-off reviews.
-   Collaborate with Design Verification, DFT, Physical Design, Synthesis, Architecture, and other engineering teams.
-   Support design quality, integration milestones, sign-off activities, and **tapeout readiness**.
-   Mentor junior engineers and contribute to improving RTL integration methodologies and best practices.

### WHAT MAKES YOU A GREAT FIT

-   **7+ years of experience** in RTL design, RTL integration, SoC integration, or semiconductor product development.
-   Strong hands-on expertise in **RTL Integration and Verilog/SystemVerilog**.
-   Strong understanding of digital design concepts, RTL coding, module hierarchy, interfaces, and SoC architecture.
-   Proven experience integrating complex IPs and building large-scale **SoC/subsystem-level RTL**.
-   Strong knowledge of **AMBA protocols**, including AXI, AHB, and APB.
-   Experience with processor, memory, interconnect, PCIe, Ethernet, or other complex SoC IP integration.
-   Strong understanding of **clock-domain crossing, reset-domain crossing, lint, structural checks, and low-power concepts**.
-   Experience with static verification and RTL-quality tools such as **SpyGlass, Questa CDC, or equivalent**.
-   Good understanding of synthesis, timing analysis, **SDC constraints**, and physical-design considerations.
-   Experience handling functional and timing **ECOs** and supporting tapeout activities.
-   Strong scripting and automation skills using **Python, TCL, Perl, or Shell**.
-   Excellent debugging, analytical, and problem-solving abilities.
-   Strong understanding of semiconductor development flows from **RTL integration through verification, synthesis, physical design, and tapeout**.
-   Ability to work effectively with cross-functional engineering teams and communicate technical issues clearly.
-   Experience mentoring engineers and taking ownership of complex technical deliverables.
-   Bachelor's or Master's degree in **Electrical Engineering, Electronics & Communication, VLSI, Computer Engineering, or a related discipline** is preferred.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/B29BF80403/apply)

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