# Static Timing Analysis (STA) Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-08-21

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of Weekday’s clients**

  
Min Experience: 4+ years  
Location: Bengaluru, Karnataka  
JobType: full-time

We are looking for an experienced **Static Timing Analysis (STA) Engineer** to drive pre-layout and post-layout timing analysis and ensure timing closure across block-level and full-chip designs. The ideal candidate will have strong expertise in timing signoff, SDC constraints, MCMM analysis, variation methodologies, and clock analysis, with hands-on experience using **Synopsys PrimeTime and Tcl**.

## Requirements

### Key Responsibilities

-   Perform **pre-layout and post-layout STA** for block-level and full-chip designs.
-   Drive timing analysis and signoff across multiple design stages through tapeout.
-   Develop, review, and optimize **SDC timing constraints**.
-   Perform **MCMM (Multi-Corner Multi-Mode)** timing analysis and signoff.
-   Analyze and address **setup and hold timing violations** to achieve complete timing closure.
-   Perform **OCV, AOCV, and POCV** analysis for accurate timing signoff.
-   Conduct detailed clock analysis, including clock latency, skew, uncertainty, and timing interactions.
-   Identify timing bottlenecks and work closely with RTL, Physical Design, DFT, and other engineering teams to resolve issues.
-   Develop and maintain Tcl-based automation for STA analysis and reporting.
-   Support full-chip timing signoff activities and ensure design readiness for tapeout.
-   Collaborate with cross-functional and geographically distributed engineering teams throughout the implementation cycle.

### Required Skills & Qualifications

-   Strong hands-on experience in **Static Timing Analysis (STA)**.
-   Expertise in **Synopsys PrimeTime**.
-   Strong knowledge of **SDC constraints and timing methodologies**.
-   Experience with **setup/hold analysis and timing closure**.
-   Hands-on experience with **MCMM, OCV, AOCV, and POCV**.
-   Strong **Tcl scripting** skills.
-   Understanding of clock analysis and timing signoff methodologies.
-   Experience working with RTL, Physical Design, and DFT teams in advanced semiconductor design environments.

### Must-Have Skills

-   STA
-   PrimeTime
-   Timing Closure

### Good-to-Have Skills

-   Full-Chip STA
-   SDC
-   Tcl Scripting
-   MCMM
-   OCV/AOCV/POCV
-   Clock Analysis & Signoff

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/B5BD4D4763/apply)

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