# FPGA Design Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-09-10

**Salary:** INR 100,000–1,200,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟭𝟮𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭-𝟭𝟮 𝗟𝗣𝗔)

Experience: 3+ yrs

Location: Bengaluru

Job Type: Full-time

We are looking for an experienced **FPGA Wireless Communication Protocol Design Engineer** to develop, implement, and validate wireless communication algorithms on FPGA platforms. The role involves taking wireless communication algorithms from **high-level MATLAB/Simulink modelling through fixed-point optimisation, RTL generation, synthesis, timing closure, FPGA implementation, and hardware validation**.

The ideal candidate will have a strong foundation in **digital signal processing, wireless communication, FPGA design, and model-based development**, with a passion for building and deploying high-performance communication systems.

## Requirements

Key Responsibilities

-   Develop and validate wireless communication signal chains using **MATLAB and Simulink**.
-   Model and simulate communication algorithms including **modems, equalizers, channel coding, source coding, carrier synchronisation, and frame synchronisation**.
-   Translate floating-point communication algorithms into hardware-efficient **fixed-point implementations**.
-   Optimise fixed-point designs to achieve the right balance between **FPGA resource utilisation, computational performance, latency, and BER**.
-   Use **MathWorks HDL Coder** and model-based design methodologies to generate synthesizable RTL.
-   Develop and integrate **VHDL, Verilog, or SystemVerilog** implementations for FPGA-based wireless communication systems.
-   Design, integrate, and validate custom wireless **IP blocks** within complete FPGA signal chains.
-   Develop and integrate interfaces based on **AXI4-Stream and AXI4-Lite** architectures.
-   Perform FPGA synthesis, implementation, placement, routing, and **timing closure** using AMD/Xilinx Vivado.
-   Perform FPGA hardware bring-up, debugging, and functional verification.
-   Validate wireless communication performance using appropriate **RF test equipment** and laboratory setups.
-   Work closely with RF and hardware teams during integration, testing, and system-level validation.
-   Analyse implementation results and optimise designs for performance, resource utilisation, and reliability.
-   Troubleshoot issues across algorithm models, RTL, FPGA implementation, and hardware validation.
-   Document algorithms, models, design decisions, implementation results, test procedures, and validation outcomes.
-   Contribute to continuous improvement of wireless communication architectures, development methodologies, and FPGA implementation practices.

What Makes You a Great Fit

-   **3+ years of hands-on experience** in FPGA design, wireless communication, DSP, or related engineering domains.
-   Strong understanding of **wireless digital communication systems** and digital signal-processing concepts.
-   Hands-on experience with **MATLAB and Simulink** for algorithm modelling and simulation.
-   Strong knowledge of **fixed-point modelling and optimisation**, preferably using Fixed-Point Designer.
-   Experience with **model-based design and HDL generation** methodologies.
-   Strong programming experience in **Verilog, SystemVerilog, or VHDL**.
-   Practical experience with **AMD/Xilinx Vivado Design Suite**, including synthesis, implementation, timing analysis, and FPGA deployment.
-   Strong understanding of **OFDM, analog and digital modems, DDC/DUC, FIR/IIR filters, and digital signal processing**.
-   Experience working with **AXI4-Stream and AXI4-Lite** interfaces.
-   Understanding of FPGA resource optimisation, latency, throughput, timing closure, and hardware implementation constraints.
-   Experience with FPGA hardware bring-up, debugging, and validation using laboratory or **RF test equipment**.
-   Experience with **AMD/Xilinx Zynq UltraScale+ RFSoC** platforms is highly desirable.
-   Ability to translate theoretical DSP and wireless algorithms into practical, deployable hardware implementations.
-   Strong analytical and problem-solving skills with attention to algorithm accuracy and hardware performance.
-   Strong collaboration skills and ability to work effectively with **DSP, FPGA, RF, hardware, and system engineering teams**.
-   A **M.Tech / M.E. in Digital Signal Processing, Telecommunications, VLSI, Electronics, or a related discipline**is preferred.
-   Advanced training or certification in **DSP algorithms, wireless communication, FPGA design, or model-based development** is an advantage.
-   Strong passion for **wireless communication system design, algorithm development, FPGA implementation, and continuous technical learning**.
-   Ability to take ownership of technical challenges and deliver practical engineering results within defined timelines.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/C23F2363DD/apply)

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