# STA / Synthesis Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-08-11

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

Min Experience: 6+ years

Location: Bengaluru, Karnataka, India  
JobType: full-time

We are looking for an experienced **STA / Synthesis Engineer** with **6–12 years of experience** in digital VLSI design, timing analysis, synthesis, and design sign-off. The ideal candidate will have strong hands-on expertise in **Static Timing Analysis (STA), Design for Test (DFT), Lint, Clock Domain Crossing (CDC), synthesis, and timing closure** across block-level and top-level designs.

You will work closely with RTL, design, physical design, DFT, SoC, and verification teams to understand design requirements, implement timing constraints, analyze timing behavior, and drive successful timing closure. The role requires a strong understanding of industry-standard EDA tools and methodologies, with practical experience in **Tempus and PrimeTime**.

## Requirements

### Key Responsibilities

-   Perform **Static Timing Analysis (STA)** for complex digital designs and identify timing violations, bottlenecks, and potential design issues.
-   Work closely with design teams to understand design requirements, timing specifications, operating conditions, and implementation constraints.
-   Develop, write, and implement **block-level and top-level timing constraints** for synthesis and STA.
-   Perform synthesis and timing analysis across various design stages and ensure timing requirements are met.
-   Drive **STA and timing closure using MMMC (Multi-Mode Multi-Corner)** methodologies for both functional and DFT modes.
-   Work with industry-standard STA tools, preferably **Cadence Tempus and Synopsys PrimeTime**, for timing analysis, debugging, and sign-off.
-   Analyze setup, hold, recovery, removal, clock skew, and other timing-related issues and work with relevant teams to resolve violations.
-   Perform **SDF generation and validation** and support the functional verification team during **Gate-Level Simulation (GLS)**.
-   Generate and validate **ETM (Extracted Timing Model)** and other timing models at the IP level.
-   Support IP integration and collaborate with **SoC teams** to ensure IP timing requirements are correctly understood and met at the SoC level.
-   Perform and support **Lint and CDC analysis**, identify violations, and coordinate with RTL/design teams for resolution.
-   Support DFT-related timing analysis and ensure timing constraints and analysis are correctly implemented across DFT operating modes.
-   Participate in design sign-off activities, methodology improvements, and timing-quality reviews.
-   Debug complex timing issues and provide actionable recommendations to design and implementation teams.

### Must-Have Skills

-   **6–12 years of relevant experience** in STA, synthesis, or digital VLSI design.
-   Strong hands-on experience in **Static Timing Analysis (STA)**.
-   Strong understanding and practical experience with **DFT** methodologies.
-   Experience with **Lint and CDC** analysis.
-   Good understanding of timing concepts including setup/hold, clock uncertainty, skew, latency, timing exceptions, and multi-corner analysis.
-   Hands-on experience with **MMMC-based STA and timing closure**.
-   Experience with **Tempus and/or PrimeTime**, preferably both.
-   Strong understanding of synthesis flows and timing constraints.

### Good-to-Have Skills

-   Experience developing **block-level and top-level constraints**.
-   Experience with **SDF generation and validation**.
-   Exposure to **Gate-Level Simulation (GLS)** and functional verification support.
-   Experience in **ETM/timing model generation and validation** at the IP level.
-   Experience supporting **IP timing at SoC level** and working closely with SoC integration teams.
-   Experience handling both **functional and DFT modes** during timing closure.
-   Strong scripting/debugging skills using tools such as **Tcl, Python, or Perl**.

### Education

Bachelor’s or Master’s degree in **Electronics, Electrical Engineering, VLSI, Microelectronics, or a related field**.

### What You’ll Bring

The ideal candidate is a strong problem solver with a deep understanding of digital timing methodologies, excellent debugging skills, and the ability to collaborate effectively across RTL, DFT, physical design, verification, and SoC teams. You should be comfortable working on complex designs and driving timing closure from block-level analysis through SoC integration and sign-off.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/C413C6C814/apply)

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