# Lead RTL Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-06-24

**Salary:** INR 500,000–2,000,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

**This role is for one of the Weekday's clients**

**Salary range: Rs 500000 - Rs 2000000 (ie INR 5-20 LPA)**

Experience: 5+ yrs

Location: Bengaluru

Job Type: full-time

We are seeking a highly skilled RTL Design Lead to drive the implementation of a high-performance signal-processing ASIC featuring a multi-core vector processor and custom ISA. This is a hands-on technical leadership role where you will own the RTL development flow from architecture specification through tapeout-ready netlist, bridging the gap between system architects and RTL engineering teams.

## Requirements

Key Responsibilities

-   Translate architecture specifications into high-quality, synthesizable SystemVerilog RTL.
    
-   Define and enforce RTL coding standards, linting rules, and design methodologies.
    
-   Lead and mentor a team of RTL engineers through the complete ASIC design lifecycle.
    
-   Own the synthesis flow using tools such as Design Compiler or Genus and drive timing closure activities.
    
-   Develop and maintain SDC timing constraints.
    
-   Review RTL submissions for correctness, synthesizability, timing robustness, and coding quality.
    
-   Collaborate with physical design and external partners for GDSII handoff, including netlists, constraints, and floorplan guidance.
    
-   Work closely with verification teams to debug issues and achieve coverage closure.
    
-   Drive technical decisions related to datapath, processor, and performance-critical design blocks.
    

What Makes You a Great Fit

-   7+ years of hands-on RTL design experience using SystemVerilog.
    
-   Proven experience taking at least one ASIC through tapeout to GDSII.
    
-   Strong expertise in RTL design, synthesis, and timing closure using tools such as Design Compiler/Genus and PrimeTime/Tempus.
    
-   Background in processor, DSP, vector processing, or datapath-intensive designs.
    
-   Experience working with advanced semiconductor process nodes (28nm or below).
    
-   Excellent RTL review skills with the ability to identify timing hazards, FSM issues, and non-synthesizable constructs.
    
-   Ability to lead a small engineering team while remaining deeply involved in hands-on development.
    
-   Experience with VLIW/vector processors, deterministic architectures, SVA/formal verification, or FPGA prototyping (Vivado) is a strong plus.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/E8B72480D2/apply)

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