# DFT Engineer

> Weekday AI · Bengaluru, India · Full-time · Posted 2026-09-16

**Salary:** INR 1,500,000–3,500,000

**Workplace:** on_site

**Department:** Weekday's Client via platform

## Description

𝗧𝗵𝗶𝘀 𝗿𝗼𝗹𝗲 𝗶𝘀 𝗳𝗼𝗿 𝗼𝗻𝗲 𝗼𝗳 𝘁𝗵𝗲 𝗪𝗲𝗲𝗸𝗱𝗮𝘆'𝘀 𝗰𝗹𝗶𝗲𝗻𝘁𝘀

𝗦𝗮𝗹𝗮𝗿𝘆 𝗿𝗮𝗻𝗴𝗲: 𝗥𝘀 𝟭𝟱𝟬𝟬𝟬𝟬𝟬 - 𝗥𝘀 𝟯𝟱𝟬𝟬𝟬𝟬𝟬 (𝗶𝗲 𝗜𝗡𝗥 𝟭𝟱-𝟯𝟱 𝗟𝗣𝗔)

Experience: 7+ yrs

Location: bangalore

Job Type: Full-time

We are looking for an experienced **DFT Engineer** with strong hands-on expertise in **Design for Testability (DFT)** for complex ASIC and SoC designs. The role focuses on developing and implementing DFT architectures, scan insertion, scan-chain implementation, MBIST, ATPG, test-pattern generation, and DFT verification.

The ideal candidate will have a strong understanding of semiconductor test methodologies and the ability to own DFT activities across the design lifecycle, from architecture and implementation through pattern generation, verification, coverage analysis, and sign-off.

## Requirements

### KEY RESPONSIBILITIES

-   Develop and implement **DFT architectures** for complex ASIC and SoC designs.
-   Define and implement **scan architecture, scan insertion, and scan-chain structures**.
-   Develop, debug, and validate **ATPG patterns** for stuck-at, transition, and other fault models.
-   Implement and verify **MBIST** solutions for embedded memories.
-   Analyse and improve test coverage, fault simulation results, and pattern quality.
-   Perform DFT rule checks and identify and resolve DFT-related design violations.
-   Integrate DFT logic into RTL and netlist flows while ensuring compatibility with synthesis and physical implementation.
-   Debug scan-chain, ATPG, MBIST, test-coverage, and pattern-simulation issues.
-   Support scan-chain diagnosis and DFT-related design debugging.
-   Collaborate with RTL, Design Verification, Physical Design, STA, and Silicon Validation teams.
-   Support DFT verification, ATPG pattern simulation, and silicon bring-up activities.
-   Review DFT requirements and contribute to overall **test strategy and methodology development**.
-   Analyse fault coverage and identify opportunities to improve test quality and efficiency.
-   Support DFT implementation through synthesis, physical design, timing, and sign-off stages.
-   Prepare and maintain DFT documentation covering architecture, implementation, coverage, debug results, and sign-off.
-   Contribute to DFT methodology improvements, automation, and best practices across projects.

### WHAT MAKES YOU A GREAT FIT

-   **7+ years of hands-on experience** in **DFT / Design for Testability** for ASIC, SoC, or semiconductor products.
-   Strong practical expertise in **MBIST, ATPG, Scan Insertion, and Scan Architecture**.
-   Proven experience with scan-chain design, implementation, debugging, and validation.
-   Strong understanding of ATPG fault models, including **stuck-at and transition faults**.
-   Experience analysing test coverage, fault simulation, and ATPG pattern quality.
-   Strong knowledge of **DFT rule checking** and resolving DFT-related violations.
-   Hands-on experience with MBIST implementation and verification for embedded memories.
-   Strong understanding of DFT verification, pattern simulation, and test-pattern debugging.
-   Good knowledge of **ASIC/SoC DFT methodologies and semiconductor test flows**.
-   Understanding of the **RTL-to-GDSII flow** and DFT interaction with synthesis, STA, and physical design.
-   Experience working with industry-standard **DFT and ATPG tools** is highly desirable.
-   Strong debugging, analytical, and problem-solving skills.
-   Ability to work effectively with cross-functional semiconductor engineering teams.
-   Strong communication and documentation skills with the ability to clearly explain DFT issues and implementation decisions.
-   Ability to take ownership of DFT activities from architecture and implementation through **coverage, verification, and sign-off**.
-   Bachelor's or Master's degree in **Electrical Engineering, Electronics & Communication, VLSI, Microelectronics, or a related discipline** is preferred.

## Apply

[Apply at Weekday AI](https://apply.workable.com/weekday-1/j/EF478BDE8A/apply)

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